As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
FIG. 1 illustrates a block diagram of a conventional portable information handling system 100. As shown in FIG. 1, information handling system 100 includes a charger circuit 160 and smart battery pack 165 that are coupled in a narrow voltage DC (NVDC) circuit architecture to selectably supply power 115 through a common power node (B+) to various components of a system load 120. Components of system load 120 include a host programmable integrated circuit (e.g., CPU) 105 coupled to receive regulated power via a buck converter or voltage regulator (VR) 1421, system memory (DRAM) 116 coupled to receive regulated power via a buck VR 1422, embedded controller (EC) 180 coupled to receive power via a buck VR 1423 and other possible power-consuming components 135 (storage drives, non-volatile memory, network interface controller, etc.) that are each coupled to receive regulated power from a respective buck VR 142, which are represented by three dots and buck VR 142N. As shown, system load 120 also includes a display device 125 (e.g., LED, OLED or LCD touch screen or video monitor display) that employs backlight circuitry coupled to receive regulated power via a boost converter or VR 140 for illuminating a display panel in order to display visual images and information to a user. As shown, separate components of system load 120 are communicatively coupled together by a digital data communication bus 187.
As shown in FIG. 1, embedded controller (EC) 180 is coupled to charger circuit 160 and battery pack 165 by system management bus (SMBus). Charger circuit 160 is coupled via an input power switch 170 to an external AC adapter 155 that receives power from AC mains 150. As shown, AC adapter 155 is removably coupled to, and separable from, charger circuit 160 of information handling system 100 at mating interconnection terminals in order to provide information handling system 100 with a source of DC power to supplement DC power provided by battery cells 124 of a battery system in the form of the smart battery pack 165, e.g., lithium ion (“Li-ion”) or nickel metal hydride (“NiMH”) battery pack including one or more rechargeable batteries and a battery management unit (BMU) 166 that includes an analog front end (“AFE”) and microcontroller. As shown, a battery system data bus (SMBus) is also coupled to smart battery pack 165 to provide battery state information, such as battery voltage and current information, from BMU 166 of smart battery pack 165 to EC 180. Charger circuit 160 of information handling system 100 may also provide DC power for recharging battery cells of the battery system 165 during charging operations. A battery charging switch 181 is coupled as shown to allow charger circuit 160 to control battery charging current provided to battery cells 124. BMU 166 is coupled to current sense resistor 190, and is coupled to control charging of battery cells 124 by battery pack current switch 184 to control flow of charge current to battery cells 124 of battery pack 165, and to also control flow of discharge current from battery cells 124 of battery pack 165. In the case where battery pack 165 is replaceable, mating interconnection terminals may be provided as shown for coupling battery pack 165 to exchange current with charger circuit 160 and system load 120, and to exchange SMBus signals with EC 180.
FIG. 2 illustrates a more detailed view of a conventional arrangement of charger circuit 160 coupled to smart battery pack 165 and system load 120 in a NVDC architecture. As shown, DC IN power is provided at 20 volts DC via input power switch circuit 170 to charger circuit 160, which includes a charger chip or integrated circuit (IC) 209 that monitors total input current (and power) using current sense resistor 103. The 20 volt DC IN power is provided as shown to switch circuit 110 that includes a high side metal oxide semiconductor field effect transistor (MOSFET) that is switched on and off by charger IC 209 to provide switched current to inductor (choke) 119 in order to step down the 20 volt DC IN power to the voltage of battery cells 124, which in this case is 8.4 volts. This stepped down DC IN power is provided with output power from battery cells 124 to the common power node B+ which feeds power 115 to all voltage regulators (VRs), i.e., the buck VRs 142 and boost VR of system load 120. Thus, all system power and battery charging power is sourced from the high side MOSFET and inductor 119, and all system VR's 140 and 142 are sourced by power 115 from common power node B+. Each VR transfers the 8.4 volt power level to a voltage level that each power-consuming component of system load 120 requires. To illustrate, buck VRs 142 may each step down or reduce the 8.4 voltage level of power 115 to a lower voltage level (e.g., 1.8 volts) for system load components of FIG. 1 such as CPU/PCH 105, memory 116 and EC 180, while boost VR 140 steps up or increases the 8.4 voltage of power 115 to a higher voltage level (e.g., 37.2 volts) for backlight circuitry of display 125 of the system load of FIG. 1.
In the conventional system arrangement of FIGS. 1 and 2, all system power and battery charging power is stepped down to 8.4 volts and sourced through high-side MOSFET of switch circuit 110 and inductor 119 as shown. High-side MOSFET of switch circuit 110 and inductor 119 create more heat with more current and require thermal management to force temperature down by reducing system power using CPU throttling which reduces system performance, or by reducing charging current to battery cells 124 which increases required battery charging time. Mechanical cooling solutions are also employed, such as heat pipes and graphite sheets.